Secondly , we studied the fractal coding parameters 其次研究了分形編碼的參數(shù)。
Reduced - code parameter setting in a web site 網(wǎng)站中的精簡(jiǎn)代碼參數(shù)設(shè)置
This adds the zip code parameter to the temperature object 這向temperature對(duì)象添加郵政編碼參數(shù)。
The code parameter identifies a particular 代碼參數(shù)標(biāo)識(shí)特定的
You can either hard code parameter values as specific data values or use a parameter marker a question mark 可以將參數(shù)值硬編碼為特定數(shù)據(jù)值,也可以使用參數(shù)標(biāo)記(問(wèn)號(hào)“ ? ”
The user interface integrates the function of ip address input , encryption option , voice sampling and the configuration of code parameters 其中用戶(hù)界面集成了ip輸入功能,加密選項(xiàng)功能,并可以設(shè)置語(yǔ)音采集和編碼參數(shù)。
It may in particular be an order of decreasing importance determined as a function of at least the coded parameters of the first subset 特別地,它可以是按照重要性由高到低的順序,這是由至少第一子集的編碼參數(shù)功能決定的。
Its characteristics include : operating to the coded parameter ; dealing with a series dots at the same time to protect local convergence ; possessing characteristics for parallel computation to increase calculating speed 遺傳算法的特點(diǎn)在于:對(duì)參數(shù)編碼操作;同時(shí)操作多點(diǎn),在一定程度上可以防止局部收斂;具有并行計(jì)算的特點(diǎn),可以提高計(jì)算速度。
We propose an algorithm , which integrate the shift invariance of redundant discrete wavelet transformation ( rdwt ) and the flexibility of multi - resolution motion estimation , to overcome the shift variance of dwt and get the precise motion vector . under the different code parameter , we take the proposed algorithm compared to several present algorithms , and experiment results have shown that proposed algorithm could leave less energy in the residual frames , get more precise motion vector and better reconstructed frames 文章最后在不同的編碼參數(shù)下,將所提算法與兩種傳統(tǒng)小波域運(yùn)動(dòng)估計(jì)算法作比較,根據(jù)實(shí)驗(yàn)所得數(shù)據(jù)分析,發(fā)現(xiàn)所提算法在性能上要優(yōu)于另外幾種算法,具體體現(xiàn)在運(yùn)動(dòng)估計(jì)后所得殘差幀能量更小,重構(gòu)幀客觀與主觀質(zhì)量更高。
In the fec part , rs ( reed - solomon ) code and interleave are chosen as the basic elements of the error correction system at first ; then the coding parameter and data structure are determined based on the results of matlab simulation ; at last , hdl modules are implemented in fpga using verilog hdl , test results and simulation diagrams are presented as well . in the designing process , the proper division of the modules and the cooperation between modules need a lot of consideration , and the top - down method is adopted to solve these questions 在前向糾錯(cuò)的設(shè)計(jì)部分,文章首先根據(jù)系統(tǒng)的誤比特率要求選擇了rs ( reed - solomon )碼和交織器作為前向糾錯(cuò)部分的基本構(gòu)架,再根據(jù)matlab的仿真結(jié)果得到了具體的編解碼參數(shù)和碼字結(jié)構(gòu),最后在fpga中用硬件描述語(yǔ)言veriloghdl實(shí)現(xiàn)了各個(gè)編解碼模塊,并給出了測(cè)試數(shù)據(jù)、實(shí)現(xiàn)結(jié)果及時(shí)序仿真波形圖。